1. Field of the Invention
This invention relates to a multiple reproducing repeater station system in which individual reproducing repeater stations connected in tandem use a phase locked loop (PLL) and more particularly to an improved multiple reproducing repeater station system which can achieve the combinational effect of reducing the rise time for the response of the system (hereinafter simply referred to as the system rise time) and suppressing jitters in data.
2. Description of the Related Art
The band width of the PLL has conventionally been discussed in, for example, ANSI/IEEE Std. 802,5-1985, pp 80-82. This reference publication determines the PLL band width to be 1% of the bit rate but it in no way takes into consideration a delay in data due to the repeating operation.
More particularly, the prior art reference publication takes no account of the fact that the jitter is accumulated in different ways depending upon a delay in a logical circuit (hereinafter referred to a logic delay) participating in the repeating operation. Especially where the phase-lock time of the PLL and the system rise time are both desired to be decreased in a system having a large logic delay, the problem of the jitter accumulation becomes serious, bringing about inconvenience that constraint is imposed on the number of repeaters used and the reduction in the system rise time is inevitably prevented.
Prolongation of the PLL phase-lock time is equivalent to narrowing the PLL band width and so narrows the capture range of a voltage controlled oscillator (VCO) used in the PLL. Accordingly, a PLL incorporating such a VCO must be particularly highly stable (against temperatures and voltage variations) and becomes costly.